HMC703LP4E【PDF 44/58 页】IC FRACT-N PLL W/SWEEPR 24QFN

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Sheet目录1996

40页 41页 42页 43页 [44页]45页 46页 47页 48页

6 - 49

HMC703LP4E

v02.0813

8 GHz fractional syntHesizer

For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824

978-250-3343 978-250-3373 fax Order On-line at www.hittite.com

Application Support: pll@hittite.com

table 22. reg 09h charge Pump register

BIT

TYPE

NAME

DEFLT

DEsCRIPTION

[6:0]

R/W

CPIdn

100

Main sink Current (20uA steps)

[13:7]

R/W

CPIup

100

Main source Current (20uA steps)

[20:14]

R/W

CPOffset

Offset current (5uA steps) - see "Charge-Pump Phase offset" for

more information.

[21]

R/W

CPsrcEn

Offset current polarity (source Offset current)

Recommended 0 in integer mode , PFDInv in FRAC modes.

[22]

R/W

CPsnkEn

Offset current polarity (sink Offset current)

Recommended 0 in integer mode ,NOT PFDInv in FRAC modes.

[23]

R/W

CPHiK

Hi Gain Mode (~4mA CP I boost depending on Vcp) - Use only

with active loop filter configurations, where Vcp is controlled to

offer better phase-noise.

table 23. reg 0ah Modulation step register

BIT

TYPE

NAME

DEFLT

DEsCRIPTION

[23:0]

R/W

MODsTEP

Fractional Modulation step size for Ramp/Phase Modulation modes

(Ignored in Integer, Normal Fractional, FM, or Exact Freq modes)

This value is signed two’s complement. Positive values ramps up,

negative values ramp down.

table 24. reg 0Bh PD register

BIT

TYPE

NAME

DEFLT

DEsCRIPTION

[2:0]

R/W

PFDDly

Dead-zone avoidance delay (0~1 ns, 3~3 ns. > 3 is unused)

[3]

R/W

PFDshort

Tie both PD inputs to Ref or Div based on phase select.

[4]

R/W

PFDInv

swap PD inputs for use in inverting loop configurations.

0- Use with a positive tuning slope VCO and passive loop filter

(default)

1- Use with a negative tuning slope, or with an inverting active loop

filter with a positive tuning slope VCO

[5]

R/W

PFDUpEn

0 will disable up pulses from propagating to the CP

[6]

R/W

PFDDnEN

0 will disable dn pulses from propagating to the CP

[7]

R/W

PFDForceUp

1 will force to the top rail.

[8]

R/W

PFDForceDn

1 will force to the bottom rail.

[9]

R/W

PFDForceMid

1 will force to mid-rail

[12:10]

R/W

PsBiassel

Ps Bias Current

[14:13]

R/W

OpAmpBiassel

OpAmp Bias Current

[16:15]

R/W

McntClkGatesel

If the quantized divide ratio is guaranteed to be within a certain

range, this feature can be enabled to reduce toggle activity and

power consumption slightly. (0: 16 to 31, 1: 16 to 127, 2: 16 to 1023,

3: 16 to max)

[17]

R/W

VDIVExt

Extend VCO Divider Output Pulse width

[18]

R/W

LKDProcTesttoCP

Muxes the lock-detect oscillator to the CP force up/dn for observa-

tion.

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